1. Field of the Invention
The invention relates in general to the field of digital systems, and, more particularly, to storage devices within digital systems. Specifically, the invention relates to a method and apparatus to identify particular storage devices within a digital system.
2. Description of the Related Art
The computer system 100 of FIG. 1 includes central processing units 105, 110, 115 that are connected to a main memory 120 through the system bus 125. The system bus 125 is generally several continuous lines with multiple branches (e.g., branches 109, 114, 116, 117). The processors 105, 110, 115 may need to manipulate some data that is stored in the main memory 120. In this case, the processor 105, for example, may apply a request to the system bus 125, and the main memory 120 may respond by applying the requested data to the system bus 125. The processor 105 may store the requested data in local, high-speed storage devices 106-108, such as cache memories. A cache memory controller keeps track of the information copied into the cache memory. When the processor initiates a memory access cycle, the cache controller determines if it has a copy of the requested information in cache memory. If a copy is present, it immediately responds by sending it back to the processor or modifying it within cache memory. This is often referred to as a cache hit.
"Bus snooping" is a method used by cache subsystems to monitor memory accesses performed by other controllers of the bus. The cache controller monitors, or snoops, the system bus when another controller of the bus is performing a memory access.
In a multiprocessor system where there are several processors and several caches within each processor, as shown in FIG. 1, a MESI (Modified Exclusive Shared Invalid) cache protocol may be used to provide a method for tracking the state of a cache line. One of the MESI line states is a modify state in which a cache line contains a more recent copy than the corresponding main memory line. In this case, a modified hit occurs. When either a hit or a modified hit occurs, a hit signal or a hit-modify signal is applied to the system bus. One skilled in the art will appreciate that during normal operation, either a hit or a hit-modify signal is generated, while the generation of neither may be construed as a miss.
FIG. 2 illustrates a conventional processor 200 with internal caches 205, 210. The processor 200 is connected to the system bus 125 by lines 216 and 217. The caches 205, 210 generate cache hit signals that are applied to lines 206, 211, respectively. When the caches 205, 210 generate cache hit-modify signals, they are applied to lines 207, 212, respectively. Resolving logic 215 receives the signals generated by the caches 205, 210 and analyzes these signals to determine the valid result to be applied to the system bus 125 via the lines 216, 217. The resolving logic 215 is often employed in multiprocessor systems, such that only one hit or hit-modify signal is applied to the system bus, regardless of the number of caches within a given processor. The signal applied to the line 216 is referred to as a hit-signal instead of a cache hit signal, while the signal applied to the line 217 is referred to as a hit-modify signal.
One skilled in the art will appreciate that the common application of both the hit lines and the hit-modify lines to the system bus hinders identification of the processor and particular internal cache that has a copy of the requested data. For example, the processor 200 may apply a hit-modify signal to the bus 125 and return the requested data. Yet, there is no mechanism to identify that the processor 200 actually generated the hit-modify signal, instead of another processor (not shown). In addition, there is no mechanism to indicate that the cache 205 generated the hit-modify signal and not the cache 210. Thus, it would be beneficial to have a method and apparatus that is capable of overcoming the shortcomings of conventional methods.